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║CM:CHIP SUMMARY ║AI+0 ║LM8 ║RM75 ║PP66 ║PG62 ║VP6 ║FT3:╨AGE <> ═╙─ ├HIP ╙UMMARY ╘HE FOLLOWING SUMMARY OF CHIPS IN THE ═╙─ DRIVES IS ABSTRACTED FROM THE ═╙─ ╙ERVICE ═ANUAL FOR USE BY THOSE WITH ELECTRONICS TRAINING IN TROUBLESHOOTING. ┴DDITIONAL INFORMATION WILL BE FOUND IN THE ╙ERVICE ═ANUAL. ═╙─ ╘YPE ╙CHEMAT ╞UNCTION ╬O ╒ ---------------------------------------------------------------- 1 4016 ─IAG ┴2 ╥┴═ ├HIP $4000-47╞╞ ─IAG ┴5 2 4016 ─IAG ┴2 ╥┴═ ├HIP $4800-4╞╞╞. ─IAG ┴5 3 4016 ─IAG ┴2 ╥┴═ ├HIP $5000-57╞╞ ╞ACTORY INSTALLED ─IAG ┴5 ╙─-2 ONLY 4 4016 ─IAG ┴2 ╥┴═ ├HIP $5800-5╞╞╞ ╬OT INSTALLED; ─IAG ┴5 EXTRA ╥┴═ 5 2764 ─IAG ┴2 ╥╧═ ├HIP $├000-─╞╞╞ ─IAG ┴5 6 2764 ─IAG ┴2 ╥╧═ ├HIP $┼000-╞╞╞╞ ─IAG ┴5 7 ╥6511╤ ─IAG ┴3 ═ICROPROCESSOR ─IAG ┴5 8 ╠╙641 ─IAG ┴3 ┬IDIRECTIONAL, OPEN COLLECTOR, RECEIVER/- ─IAG ┴5 DRIVER FOR SERIAL BUS. ─IRECTION SELECTED BY ╨ORT ─ ┬IT 3 (┬5) 9┴/├ 7438 ─IAG ┴3 ╠OGIC--SEC ┴: WRAP AROUND FOR SERIAL ┴╘╬ ─ WHEN ╥6511╤ IS BUSY. ─ISABLED BY ┴╘╬┴├╦, ─IAG ┴5 ╨ORT ┴ BIT 1 (┬5). ╙ECS ├ AND ─ WRAP AROUND FOR ╔┼┼┼ ┴╘╬, ALSO DISABLED BY ╨ORT ┴ BIT 1 (┬6) 10┴/├ ╠╙02 ─IAG ┴3 ╠OGIC--╙ECS ┴/├ ASSERT ╥┼╙┼╘ FROM ╔╞├ ┬/─ ─IAG ┴4 SERIAL OR ╔┼┼┼ INTERFACES (┬3) ─IAG ┴5 11 7406 ─IAG ┴4 ╠OGIC--INTERFACE SIGNAL DRIVER: OPEN 11┬ ─IAG ┴4 COLLECTOR WITH 150 OHM PULL-UPS FOR MOTOR ─IAG ┴5 AND HEAD STEPPING (┬6) 12 ╠╙193 ─IAG ┴4 ─ATA BIT COUNTER USING ╒13 CLOCK (┬2). ─IAG ┴5 ╙YNCHRONIZED TO ╥/╫ DATA STREAM BY SIGNAL FROM ╒30┴. ╠OADED WITH ╞╥┼╤┴ AND ╞╥┼╤┬ SIGNALS FROM ╒25 TO SET BIT DENSITY (┬7). ╙ET TO FREE RUN DURING WRITE BY DISABLED ╒30┴. 13 ╠╙163 ─IAG ┴3 ├LOCK/─IVIDER: ├OUNTER FOR 2 MHZ FROM ─IAG ┴5 ╒26 (┬2) 14┼/╞ 7406 ─IAG ┴2 ╠OGIC--INTERFACE SIGNAL DRIVER: OPEN ┴/┬ ─IAG ┴2 COLLECTOR WITH 150 OHM PULL-UPS. ╙ECS ├/─ ─IAG ┴4 ├ AND ─ FOR WRITE GATE AND DATA; SECS ─IAG ┴5 ┴, ┬, ┼, AND ╞ FOR ╠┼─'S (┬6) 15 ╠╙193 ─IAG ┴4 ─ATA GENERATOR COUNTER: BIT CLOCK FOR ╒20. ─IAG ┴5 ├LEARED BY PULSE FROM ╒30┴ (┬8). 16 ╠╙163 ─IAG ┴4 ┬YTE COUNTER. ╙TROBES BYTE INTO ╨ORT ┬; ─IAG ┴5 SIGNALS BYTE READY TO PROCESSOR. ─ISABLED BY ╙┘╬├. ┴T DATA BIT 8, ╤├ GOES LOW TRIGGERING ╒30┬ WHEN ╤─ IS LOW (┬9). ╔N WRITE MODE, SIGNALS PROCESSOR TO PUT NEXT BYTE IN ╨ORT ┬. ╫HEN ╤─ GOES HIGH NEXT BYTE IS LOADED INTO SHIFT REGISTER. 17┴/┬ ╠╙139 ─IAG ┴2 ╙EC ┴ DECODES ADDRESS FROM ╒18 TO SELECT ─IAG ┴5 ╥┴═ CHIP (┬3). ╙EC ┬ PROVIDES LOW WRITE PULSE FOR 6511╤ TO WRITE DATA TO ╥┴═ (┬3) 18 ╠╙138 ─IAG ┴2 ─ECODES ADDRESS FROM ╥6511╤ FOR ╥┴═/╥╧═ ─IAG ┴5 (┬3) 19 ╠╙153 ─IAG ┴4 ╠OGIC--13 INPUT NAND GATE: SYNC DETECTOR ─IAG ┴5 (┬9) ╥/╫. ╙┘╬├ SIGNALLED WHEN 10 "1" BITS OCCUR IN A ROW WHEN ╫╥╔╘┼╬* IS HIGH; SIGNALLED THROUGH ╒22-12 (┬9) 20 ╠╙299 ─IAG ┴4 ╙HIFT REGISTER--RECEIVES DATA STREAM ─IAG ┴5 FROM ╒15-╤├ CLOCKED BY ╒15-╤─ BIT CLOCK FOR ╥/╫ (┬8). ╨ARALLED OUTPUT ENABLED BY ╙╥╥─┼╬* LOW TO CREATE 40 "1" BITS FOR SYNC. ╙YNC OVERFLOWS TO ╒23. 21 ╠╙611 ─IAG ┴3 ┬IDIRECTIONAL DRIVER/RECEIVER FOR ╔┼┼┼. ─IAG ┴5 ─IRECTION SET BY ╨ORT ─, ┬IT 3 (┬6) 22 ╠╙240 ─IAG ┴3 ┼NABLED BY ╙╘┴╘╔╬┼╬* SIGNAL FROM ╒25. ─ ─IAG ┴4 ╥EADS WRITE PROTECT AND TRACK00 SIGNALS ─IAG ┴5 ON 6511╤ ╨ORT ┬ BUS. ╥EADS DEVICE NUMBER 22┴/├ ╠╙240 ─IAG ┴3 ON ╩┬1 JUMPER BLOCK (┬7). ╙EC ─: ╙┘╬├ ┬ ─IAG ┴4 SIGNAL ON PIN 12 FROM ╒19 HIGH SENT TO ╨ORT ┴ ┬IT 6 (┬9). ╙EC ├: ╔NVERTER FOR ┴╘╬┴├╦. 23┴/┬ ╠╙74 ─IAG ┴4 ┼XTENDED SHIFT REGISTER FOR 10 BIT ╟├╥ ─IAG ┴5 CODE AND SYNC FROM ╒20 (┬9) ╥/╫. 24┴/┬ ╠╙14 ─IAG ┴3 ╠OGIC--╙EC ┴: ╘IMER TRIGGER FOR ╥┼╙┼╘ ├/─ THROUGH CAPACITOR ├11 (┬2). ╙EC ┬, ├, ─: ┼/╞ ─IAG ┴4 ╔NVERTERS FOR ╔┼┼┼ ╔╞├*, ╔┼┼┼ ┴╘╬, AND ─IAG ┴5 ╙ERIAL ┴╘╬. 25 ╠╙174 ─IAG ┴2 ╠ATCH FOR DATA FROM ╥6511╤--WRITTEN TO ─IAG ┴5 WHEN ╠╙╘┬* SIGNAL GOES LOW (┬3). ╞╥┼╤┴ AND ╞╥┼╤┬ SIGNALS PROVIDED TO ╒12 TO SET BIT DENSITY FOR ╥/╫ (┬8); ╙╘┴╘╔╬┼╬ FOR ╒22 ENABLE; ╠┼─ SIGNALS 26┼ ╠╙04 ─IAG ┴2 ╠OGIC. ╧SCILLATOR: ╔NVERTERS DRIVEN BY ┴/┬/╞ ─IAG ┴3 16 M╚Z CRYSTAL (┬2). ╙EC ╞: OSC BUFFER. ├/─ ─IAG ┴4 ╙EC ├/─: ╔NVERTERS FOR ╒15; ╙EC ┼ FOR ╒18. ─IAG ┴5 27├/─ ╠╙02 ─IAG ┴4 ╠OGIC--╙HIFT CLOCK(?)--╒SED TO CREATE ┴/┬ ╫╥╔╘┼ ─┴╘┴* FROM "1" PULSES FROM ╒20 (┬10). ─IAG ┴5 ╙EC ├: ┴╬─ GATE FOR ╒16; ╙EC ─ FOR ╒15 ─ATA/├LOCK. 28┴/┬ ╠╙74 ─IAG ┴4 ╫RITE GATE, BYTE TEST ─IAG ┴5 29├/─ ╠╙00 ─IAG ┴2 ╠OGIC GATE. ╙EC ┴--╫╥╔╘┼ ╟┴╘┼ ENABLES ┴/┬ ─IAG ┴4 PARALLEL LOADING FROM ╨ORT ┬ WHEN ╫╥╔╘┼╬* ─IAG ┴5 IS LOW. ╙EC ├: ┴╬─ GATE FOR ╒25 ╠╙╘┬*; ╙EC ─ FOR ╒17┬ WRITE PULSE 30┴/┬ ╠╙221 ─IAG ┴4 ╧NE-SHOT--SEC ┴ NARROWS ╥┼┴─ ─┴╘┴* SIGNALS ─IAG ┴5 TO 80 NS FOR DISK READ (┬8) USED BY ╒12 AND ╒15. ╙EC ┬ GENERATES 12 USEC ┬┘╘┼╥╤ SIGNAL ON ╨ORT ┴, BIT 7 WHEN ╤├ GOES LOW AND ╤─ FROM ╒16 IS LOW (┬9). ╙EC ┴ DISABLED BY ╫╥╔╘┼╬*=0 FOR WRITE TO FREE RUN ╒12 (┬10). 31┼ ╠╙14 ─IAG ┴3 ╠OGIC--╔NVERTERS. ╙EC ┴/┬ FOR ╫╥╔╘┼╬*; ┴/─/╞ ─IAG ┴4 ╙EC ┼ FOR ╙ERIAL ╔╞├*; ╙EC ╞ FOR ╥EAD ─ATA ─IAG ┴5 ---------------------------------------------------------------- ┬ASED ON THE ═╙─ ╙UPER ─ISK ─RIVE ╞UNCTIONAL ─ESCRIPTION SECTION OF THE ═╙─ ╙ERVICE ═ANUAL DATED ╩ANUARY 27, 1984. ╘HE ┬ NUMBERS REFER TO PAGES IN THE SECTION. ╘HE ┴ NUMBERS REFER TO THE SCHEMATICS FOUND IN ┴PPENDIX ┬ OF THE ╙ERVICE ═ANUAL. ┴SSEMBLED BY THE ═╙─ ╔NFORMATION ┼XCHANGE, ╨AUL ┼. ┼CKLER, 2705 ╚ULMAN ╙T., ╘ERRE ╚AUTE, ╔╬ 47803, 812-234-8240, 812-232-0121 ---------------------------------------------------------------- ╧CTOBER 19, 1986 
